ECE 351

syllabus

Homework #1 (SRAM) Due 10-13-2008 
Homework 2 is delayed until 10-27-2008 

Supplementary Material

1. ASIC primer
2. ASIC and ASSP definitions
3. RTL definition
4. IP
   • Minimum/Maximum Value IP datasheet.
   • Parity generator IP datasheet.
   • Decoder IP datasheet
   • Lattice 1553 encoder/decoder IP datasheet.
5. CoreGen overview
6. Test bench basics
7. force/release timing diagrams and programs for nets and regs.
8. Verification definitions
9. A brief standard cell overview.
10. Here is a list of cells found in a typical standard cell library.
11. FPGA overview
12. FPGA/ASIC design flow
13. Lattice FPGA synthesis guidelines
14. RTL closure
15. RTL coding hints
16. FIFO example
17. FPGA programming via JTAG (pages 1-6, 12)
18. FPGA via SPI (pages 1-7)
19. JTAG download cable
20. JTAG download cable schematic
21. FPGA programming via parallel EPROM
22. SPI programming schematic
23. Lattice Semiconductor datasheet
24. Xilinx FPGA (3 files) file 1, file 2, file 3

Items of Interest

1. Is VHDL a dead language? (see this article)
2. An excellent EDA introduction article
3. Verilog code examples
4. If vs. case statement synthesis
5. Intro to scripts

Using the Verilog compiler/simulator. You can add signals to the simulator timing diagram by following this procedure.

Using the FPGA synthesizer.

1. Start with the FPGA quick tutorial. Go to the full tutorial only if needed.
2. The quick tutorial refers to a pin assignment table. That link is broken. You can obtain the pin assignments here.